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[Other resource] addch1

Description: 用vhdl语言设计CPU中的一部分：加法器的设计，包括多种加法器的设计方法！内容为英文-design using VHDL language part of the CPU : Adder design, Adder including multiple design! As for the English
Platform: | Size: 392983 | Author: qindao | Hits:

[Other resource] mul6

Description: 用vhdl语言设计CPU中的一部分：乘法器的设计，包括多种乘法器的设计方法！内容为英文-design using VHDL language part of the CPU : multiplier design, Multiplier including multiple design! As for the English
Platform: | Size: 463599 | Author: qindao | Hits:

[VHDL-FPGA-Verilog] addch1

Description: 用vhdl语言设计CPU中的一部分：加法器的设计，包括多种加法器的设计方法！内容为英文-design using VHDL language part of the CPU : Adder design, Adder including multiple design! As for the English
Platform: | Size: 393216 | Author: qindao | Hits:

[VHDL-FPGA-Verilog] mul6

Description: 用vhdl语言设计CPU中的一部分：乘法器的设计，包括多种乘法器的设计方法！内容为英文-design using VHDL language part of the CPU : multiplier design, Multiplier including multiple design! As for the English
Platform: | Size: 462848 | Author: qindao | Hits:

[Other] computer

Description: 在LP2900工作平台上，利用MAX+plusII开发软件，设计各个模块编程实现基本模型计算机，其中最主要的是CPU的设计。 独立完成运算器的设计，并下载仿真 -Working platform in the LP2900, using MAX+ PlusII to develop software, design each module to achieve the basic model of programming computers, among which is the CPU design. An independent operator to complete the design, and download the simulation
Platform: | Size: 71680 | Author: 杨继伟 | Hits:

[VHDL-FPGA-Verilog] ALU

Description: vhdl代码 使用quartus编译 cpu中 alu的设计 可作为课程设计的参考 此为16的运算器-VHDL code using Quartus compiler cpu in alu design of curriculum design can be used as a reference for this for 16 computing device
Platform: | Size: 1024 | Author: 闵瑞鑫 | Hits:

[OS program] 16cpu

Description: 实现16位的cpu设计 内容使用verilog hdl实现，具体的实现步骤方法，都已经写到文档里面去了！-To achieve 16-bit design of the contents of the cpu using verilog hdl achieve, the specific methods to achieve these steps have already been written inside the document went to!
Platform: | Size: 440320 | Author: gimel_sh | Hits:

[Graph Recognize] POCREPORT

Description: 为充分利用CPU的运行效率，采用中断功能设计并行输入输出接口，以达到缓解CPU高速运行速度与外设低速缓冲间的矛盾。-To take full advantage of the efficiency of CPU operation, interruption of functional design using parallel input-output interface, in order to alleviate the CPU speed and high-speed peripherals contradictions between low-speed buffer.
Platform: | Size: 209920 | Author: Rachel | Hits:

[VHDL-FPGA-Verilog] mipsfinal

Description: 用vhdl设计的一个mips小型cpu，不带流水，有r类，i类，j类指令都有~·-Using vhdl design a mips small cpu, with no running water, there are r class, i type, j class instruction have ~*
Platform: | Size: 354304 | Author: yusufu | Hits:

[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24

Description: 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下： ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段； cpuctr.v用于产生CPU控制信号； ALU.v用于对操作数进行相应指令的运算并输出结果； DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器 在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Platform: | Size: 4946944 | Author: 石 | Hits:

[Embeded-SCM Develop] CPU

Description: 利用VHDL语言 开发设计一个小型CPU -Development and design using VHDL, a small CPU
Platform: | Size: 201728 | Author: 隐士 | Hits:

[VHDL-FPGA-Verilog] NET2

Description: This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, using Veril Verilog language, a hardware-base FPGA embedded project combat, Man Application FPGA, FPGA-chip hardw Mallat implementation of wavelet Layer of one-dimensional wavelet
Platform: | Size: 1852416 | Author: sansfroid | Hits:

[VHDL-FPGA-Verilog] CPU-design

Description: 使用VHDL语言开发的CPU硬布线设计，在实验电路可以使用加法，和减法与或等简单操作-CPU using VHDL language development of hard-wired design, the circuit can be used in the experimental addition, and subtraction or other simple operations with
Platform: | Size: 2048 | Author: Han li | Hits:

[VHDL-FPGA-Verilog] vhdl_16CPU

Description: 16位CPU设计，采用VHDL语言，自带测试汇编语言，能实现基本运算和移位、跳转等操作-16-bit CPU design, using VHDL language, self-test assembly language, to achieve the basic operations and shift operations such as jump
Platform: | Size: 985088 | Author: 戈多 | Hits:

[VHDL-FPGA-Verilog] AVR_Core

Description: AVR 单片机内核处理器vhdl代码，用fpga设计的avr cpu核，主要供fpga学习者参考用-AVR microcontroller core processor vhdl code, using fpga design avr cpu core, the main reference for learners fpga
Platform: | Size: 70656 | Author: lixinping | Hits:

[VHDL-FPGA-Verilog] mips-cpu

Description: 单周期的mips处理器设计，用vhdl语言实现各个模块的功能-Single-cycle mips processor design, using vhdl language functions of each module
Platform: | Size: 117760 | Author: 王晓强 | Hits:

[VHDL-FPGA-Verilog] altera_inspector.log

Description: vhdl代码 使用quartus编译 cpu中 alu的设计 可作为课程设计的参考 此为16的运算器-VHDL -code using Quartus compiler cpu in alu design of curriculum design can be used as a reference for this for 16 computing device
Platform: | Size: 2750464 | Author: 王川 | Hits:

[VHDL-FPGA-Verilog] cpu

Description: using vhdl design cpu
Platform: | Size: 1024 | Author: Dung | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。-Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related.
Platform: | Size: 822272 | Author: wang | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 使用QuartusII软件，利用VHDL语言设计实现CPU,其中包含时序图仿真。-Using software QuartusII, using VHDL language to design the CPU, which contains sequence diagram simulation.
Platform: | Size: 2549760 | Author: 段绍丽 | Hits:

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